The present invention relates generally to low-dropout voltage regulators (LDO voltage regulators), and more particularly to LDO voltage regulators which are especially suited to being embedded in various integrated circuit chips that require precise internal load voltage regulation, and yet more particularly to improvements which provide such LDO voltage regulators with high bandwidth and fast response to instant increases (i.e. step increases) in the demanded load current without use of a large, external load bypass capacitor.
Power consumption of various digital logic circuit cells that are manufactured using various modern integrated circuit manufacturing processes can instantly, i.e., within a few picoseconds, vary between zero and a large maximum value, e.g. 5 to 150 milliamperes. At the same time, very precise power supply voltage regulation is required for the digital logic circuit cells.
Existing topologies of voltage regulator circuits do not allow sufficiently fast circuit operation to supply such large instantaneous increases, i.e. steps, in the amount of demanded load current without using large external load bypass capacitors that have capacitances in the microfarad range connected between the output of the LDO voltage regulator and a power supply conductor along with the digital logic circuit cells and the LDO voltage regulator which powers them. Such large load bypass capacitors can not, as a practical matter, be included in an integrated circuit chip. Although small load bypass capacitors having capacitances of up to a few nanofarads have been included in digital logic circuit cells, these small capacitors are incapable of supplying load current steps as large as would typically be needed. Consequently, it has been necessary to use above mentioned external load bypass capacitors.
Use of the external load bypass capacitors is costly because of the relatively high cost of the capacitors themselves, the costs associated with the extra required integrated circuit package lead, and the cost of the additional area of the bonding pad required on the integrated circuit chip in which the digital logic circuit cells and the voltage regulator are formed. Furthermore, and most important, the external load bypass capacitor is separated from the output of the embedded voltage regulator by a signal path and a wire bond connection having a parasitic inductance of roughly 3-5 nanohenrys. The voltage drop across this parasitic inductance during a load current step ordinarily exceeds the load voltage regulation requirements of the digital logic circuit cells. This causes operation of the digital circuitry powered by the embedded voltage regulator to be unreliable.
The closest prior art is believed to include the LDO voltage regulator shown in FIG. 3 of commonly owned U.S. Pat. No. 6,930,551 “Zero Voltage Class AB Minimal Delay Output Stage and Method” issued Aug. 16, 2005 to Ivanov et al. Prior Art FIG. 1 herein shows a schematic diagram of an LDO voltage regulator essentially similar to the one in FIG. 3 of the '551 patent.
In Prior Art FIG. 1, LDO regulator 1 includes a differential input amplifier stage including differentially coupled N-channel input transistors MN1 and MN2. The gate of transistor MN1 is connected to a reference voltage Vref that can be generated by a conventional bandgap circuit. The gate of transistor MN2 is connected to a conductor 6, on which the regulated output voltage Vout of LDO voltage regulator 1 is produced by means of an output stage including P-channel pass transistor MP3 and a N-channel pull-down transistor MN4, a P-channel source follower transistor MP4, and a N-channel cascode transistor MN3. The drain of input transistor MN2 is connected by conductor 3 to the gate of source follower transistor MP4 and to a terminal of a small internal capacitor C0, which provides compensation for the feedback loop that includes input transistor MN1 and source follower transistor MP4. The source and bulk electrodes of source follower transistor MP4 are connected to output conductor 6, which also is connected to the sources of P-channel active load transistors MP1 and MP2 of the differential input stage. The drain of source follower transistor MP4 is connected by conductor 8 to the gate of pull-down transistor MN4. A constant current source 11 producing a current I1 is coupled between VSS and the source of cascode transistor MN3, the drain of which is coupled by conductor 12 to the gate of pass transistor MP3 and one terminal of a pull-up resistor R, the other terminal of which is connected to VDD. The gate of cascode transistor MN3 is connected by conductor 18 to the (+) terminal of a constant voltage source 9, the (−) terminal of which is connected to VSS. Source follower transistor MP4 is part of a current gain boost feedback loop which in effect increases the output conductance of source follower transistor MP4 and increases the load drive capability of LDO regulator 1. A load 7 is connected between Vout and VSS. One terminal of external load bypass capacitor CEXT is coupled by a wire bond to regulated output voltage conductor 6. The wire bond can be represented by its 3-5 nanohenry inductance Lwb. The other terminal of external load bypass capacitor CEXT is also connected by means of a similar wire bond inductance to the VSS conductor on the integrated circuit chip. Load 7 can be represented by a variable current source IL connected in parallel with a small internal load capacitance CINT.
The circuit structure of prior art LDO voltage regulator 1 provides a large achievable small-signal bandwidth for a chosen total current consumption and a chosen integrated circuit manufacturing process, but can not provide a suitably fast large-signal response to a step increase in the current demanded by load 7 connected to the regulated output voltage Vout on conductor 6. This is because the gate voltage of pass transistor MP3, which typically is a very large device having a gate capacitance of roughly 0.5 to 10 picofarads, may need to swing from few hundred millivolts to more than a volt in response to a step increase in the current demanded by load 7, whereas the current available to charge the gate of the pass transistor MP3 during the load current step is limited by the amount of current I1 that can be supplied by current source 11 alone.
Consequently, the amount of current I1 of current source 11 must be substantially increased in order to achieve a correspondingly faster response of LDO voltage regulator 1 to a step increase in the demanded load current, thereby undesirably increasing the power consumption of prior art LDO voltage regulator 1.
Thus, there is an unmet need for LDO voltage regulator circuitry which can provide substantially increased voltage regulator bandwidth without correspondingly increased power consumption.
There also is an unmet need for LDO voltage regulator circuitry which can provide a very fast, large-swing drive signal to the gate of an output transistor of the LDO voltage regulator in response to a step-current increase in the current demanded by a load without substantially increasing the quiescent current of the voltage regulator.
There also is an unmet need for LDO voltage regulator circuitry capable of providing fast regulation response for an increased range of load capacitance.
There also is an unmet need for LDO voltage regulator circuitry capable of providing both fast regulation response and stable operation for an increased range of load capacitance.